1. Technical Field of the Invention
This invention relates to semiconductor memory devices and more particularly to non-volatile semiconductor memory devices using a ready/busy pin.
2. Description of the Related Art
In recent years, supply voltages for memory devices have been gradually lowered as integration densities become higher and the scaling-down of semiconductor memory devices continues. Consequently, it is now conventional to lower an external voltage to a predetermined voltage level that properly drives internal circuits of the memory device with the proper electrical conditions.
For the purpose of using the internal voltage into the internal circuits, many semiconductor memory devices, such as DRAM, SRAM, flash EEPROM, etc., have internal voltage generators therein. The semiconductor devices embedded within mobile systems conventionally include their own internal voltage generators in order to reduce the operative power consumption of the systems and to set appropriate levels of internal voltages lower than the external voltages.
It has thus become more important for memory devices embedded in mobile systems to operate with lower voltages and promote lengthening of battery life. The internal voltage generator typically brings a higher external voltage level down to a lower predetermined voltage level in a required time. In a basic procedure for settling the internal voltage, an external voltage is compared with a reference voltage to regularly establish a level of the internal voltage. The internal voltage may retain a constant voltage level by itself in a standby mode (or a sleep mode) of the device because there are no power transitions (or variations). But, when the memory device returns to an active mode from the standby mode, the internal voltage may accidentally drop or fluctuate because of dynamic power transitions and a multiplicity of operations by a number of internal circuit elements. Such variations of the internal voltage level may cause operational malfunctions.
Meanwhile, the power-up speed (or a setup time) of the internal voltage may be different from that of the external voltage in the internal voltage generator. Namely, the power-up speed of the external voltage is faster than that of the internal voltage, i.e., the internal voltage VINT has not reached its required voltage level yet even when the external voltage has already been set to an operable level. During this time, the internal voltage is in an unstable condition.
Referring to FIG. 1, at a time A, an external voltage VEXT has risen above a predetermined voltage VDET to a voltage level where the memory device is operable in a stable condition, hereinafter referred to as the “operation voltage level”. Although at time A the external voltage has surpassed the voltage VDET, an internal voltage VINT has not yet reached the operation voltage level VDET yet. The internal voltage VINT arrives at the operation voltage level VDET at a time B after a term TAB from the time A.
If a system simply checks a level of the external voltage VEXT at the time A where the external voltage VEXT is saturated, and then renders a memory device operable based only upon the external voltage VEXT, the memory device may be conditioned with functional instability because the internal voltage VINT has not yet reached the operation voltage level VDET.
Accordingly, for memory devices, the system needs to check whether the internal voltage VINT has reached the operation level or not.
Embodiments of the invention address these and other limitations of the conventional art.